In Chip-on-Wafer-on-Substrate (CoWoS) technology, through-silicon-vias and interconnects are utilized to integrate multiple chips into a single device. Other structures may also be included, such as dummy structures, and the formation of various features may be streamlined by being performed together. For example, multiple planarization steps may be combined into one. However, such combination may give rise to issues with metal bump height variation and overburden thickness, which may increase manufacturing costs and times.